This invention relates to an operational amplifier circuit comprising:
matched transistors forming a differential pair arrangement having a common terminal, first and second control terminals forming inputs of the amplifier and first and second output terminals;
a bias current source having an output connected to the common terminal of the differential pair arrangement;
a current mirror active load circuit having an input transistor and an output transistor connected to receive current from the first and second output terminals of the differential pair arrangement, respectively; and
at least one output transistor having a control electrode connected to the second output terminal of the differential pair arrangement, the said output transistor being arranged to supply an output current of the amplifier to a load.
Such operational amplifier circuits are well known, for example, from U.S. Pat. No. 4 287 439, and are frequently found as part of an integrated circuit in bipolar or CMOS technology, for example. The differential pair arrangement typically comprises just two matched transistors in a "long-tailed pair" configuration, but may be enhanced by the provision of further transistors, for example, in Darlington or cascode configurations. As in all differential circuits, offset errors can arise because of a random mismatch between devices. Random errors can be minimized by layout and process improvements, as is well known in the art. There are also, however, predictable or systematic offset errors, dependent on the circuit design. It is known that by suitable design and scaling of the geometries of the various devices of the amplifier, systematic offset can be compensated in certain circumstances by subtracting from the current flowing through the output transistor a bias current related to the bias current generated for the input stage.
However, the compensation of systematic offset remains accurate only on condition that no further load is driven by the output transistor. In other words, the amplifier has a high-impedance voltage output only. To drive low-impedance loads it has been necessary to add a further output stage, which not only adds to the component count and increases power dissipation, but also introduces a systematic offset error of its own. An example of an application in which this error is a problem is in the field of bandgap voltage reference circuits such as that described in U.S. Pat. No. 4 287 439.